ARM Cortex-A8
| General information | |
|---|---|
| Designed by | ARM Holdings |
| Common manufacturer | |
| Cache | |
| L1 cache | 32 KiB/32 KiB |
| L2 cache | 512 KiB |
| Architecture and classification | |
| Microarchitecture | ARMv7-A |
| Physical specifications | |
| Cores |
|
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The ARM Cortex-A8 is a 32-bit processor core licensed by ARM Holdings implementing the ARMv7-A architecture.
Compared to the ARM11 core, the Cortex-A8 is a dual-issue superscalar design, achieving roughly twice the instructions executed per clock cycle. The Cortex-A8 was the first Cortex design to be adopted on a large scale for use in consumer devices.[1]
Features
Key features of the Cortex-A8 core are:
- Frequency from 600 MHz to 1 GHz and above
- Superscalar dual-issue microarchitecture
- NEON SIMD instruction set extension [2]
- 13-stage integer pipeline and 10-stage NEON pipeline [3]
- VFPv3 Floating Point Unit
- Thumb-2 instruction set encoding
- Jazelle RCT (Also known as ThumbEE instruction set)
- Advanced branch prediction unit with >95% accuracy
- Integrated level 2 Cache (0–4 MiB)
- 2.0 DMIPS/MHz
Chips
Several system-on-chips (SoC) have implemented the Cortex-A8 core, including:
- Allwinner A1X
- Apple A4
- Freescale Semiconductor i.MX51 [4]
- Rockchip RK2918, RK2906 [5]
- Samsung Exynos 3110
- TI OMAP3
- TI Sitara ARM Processors
- Conexant CX92755 [6]
See also
- ARM architecture
- List of ARM cores
- List of applications of ARM cores
- Comparison of ARMv8-A cores
- JTAG
References
- ^ Gupta, Rahul (April 26, 2013). "ARM Cortex: The force that drives mobile devices". The Mobile Indian. Retrieved 2013-05-15.
- ^ Cortex-A8 Specification Summary; ARM Holdings.
- ^ Williamson, David, ARM Cortex A8: A High Performance Processor for Low Power Applications (PDF)
- ^ "i.MX51 Applications Processor and Linux Hands on" (PDF).
- ^ "RK29XX".
- ^ "CX97255" (PDF).
External links
- ARM Holdings