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SPARC

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Sun UltraSPARC II Microprocessor

SPARC (Scalable Processor ARChitecture) is a pure big-endian RISC microprocessor architecture originally designed in 1985 by Sun Microsystems. SPARC is a registered trademark of SPARC International, Inc., an organisation established in 1989 to promote the SPARC and to provide conformance testing. SPARC International was intended to "open" the SPARC architecture to make a larger ecosystem for the design, which has been licensed to several manufacturers, including Texas Instruments, Cypress Semiconductor, and Fujitsu. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary: there's a fully open source implementation called LEON, written in VHDL. Its source code is available under the LGPL.

Implementations of SPARC architecture were initially designed and used for workstations, and then used for larger SMP servers produced by Sun Microsystems and Fujitsu among others. SPARC machines are generally synonymous with Solaris, the operating system (OS) from Sun designed for SPARC. However various ports from operating systems like NeXTSTEP, Linux, FreeBSD, OpenBSD and NetBSD work on SPARC processors.

There have been several revisions of the architecture, the most recent being versions 8 and 9.

Features

The SPARC architecture was heavily influenced by the earlier designs of the RISC I & II from the University of California, Berkeley. These original RISC designs were minimalist, including as few features or op-codes as possible and demanding that all operations complete in one cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

The SPARC processor usually contains as many as 128 general purpose registers. At any point, only 32 of them are available - 8 are global registers and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for keeping values across function calls. The "Scalable" in SPARC comes from the fact that the SPARC specification allows up to 32 windows. So the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement minimum to reduce the context switching time. Other architectures that include similar register windows include Intel i960, IA-64, and AMD 29000.

In version 8, the floating-point register file has 16 double precision registers. Each of them can be used as two single precision registers, providing a total of 32 single precision registers. An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers. Version 9 added 16 more double precision registers, but these additional double precision registers can not be used as single precision registers.

Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format.

History

The architecture has gone through a few revisions and has gained multiply and divide functionality in version 8. The most substantial upgrade resulted in the version 9 which is a 64-bit SPARC specification.

Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, so as to be used as reference systems for SPEC CPU95 and CPU2000 benchmarks.

SPARC microprocessor specifications
Model Frequency
[Mhz]		 Architecture
Version		 Year Process
[µm]		 Transistors
[millions]		 Die size
[mm²]		 IO Pins Power
[W]		 Voltage
[V]		 L1 Dcache
[k]		 L1 Icache
[k]		 L2 Cache
[k]		 L3 Cache
[k]
microSPARC I 40-50 V8 1992 0.8 0.8 225 288 2.5 5 4 2 none none
SuperSPARC I 33-50 V8 1992 0.8 3.1 -- -- 14.3 5 20 16 0-2048 none
microSPARC II 60-125 V8 1992 0.5 2.3 233 321 5 3.3 16 8 none none
SuperSPARC II 75-90 V8 1994 0.8 3.1 299 -- 16 -- 20 16 1024-2048 none
TurboSPARC 160-180 V8 1995 0.35 -- -- 416 7 3.5 16 16 512 none
UltraSPARC I 143-200 V9 1995 0.5 5.2 315 521 30 @167MHz 3.3 16 16 512-1024 none
UltraSPARC IIs (Blackbird) 250-360 V9 1997 0.35 5.4 -- 521 25 @250MHz 2.5 16 16 1024 or 4096 none
UltraSPARC IIs (Sapphire-Black) 360-480 V9 1999 0.25 5.4 156 521 21 @400MHz 1.9 16 16 1024-8192 none
UltraSPARC IIi (Sabre) 270-360 V9 1997 0.35 5.4 148 587 21 1.9 16 16 256-2048 none
UltraSPARC IIi (Sapphire-Red) 333-480 V9 1998 0.25 5.4 -- 587 21 @440MHz 1.9 16 16 2048 none
UltraSPARC IIe 400-600 V9 2000 0.18 Al -- -- 370 13 max @500MHz 1.5-1.7 16 16 256 none
UltraSPARC IIi (Sabre+) 550-650 V9 2002 0.18 Cu -- -- 370 17.6 1.7 16 16 512 none
UltraSPARC III 600-1200 V9 2001 0.13 29 330 1368 53 1.6 64 32 8192 none
UltraSPARC IIIi 1064-1593 V9 2003 0.13 87.5 206 959 52 1.3 64 32 1024 none
UltraSPARC IV 1050-1350 V9 2004 0.13 66 356 1368 108 1.35 64 32 16384 none
UltraSPARC IV+ 1500 V9 2005 0.09 295 336 1368 90 1.1 64 64 2048 32768

See also

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