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PowerPC

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PowerPC is a RISC microprocessor architecture created by the 1991 Apple-IBM-Motorola alliance, known as AIM. The PowerPC was the CPU portion of the overall AIM platform, and is the only part to exist to date.

History

The history of the PowerPC begins with IBM's POWER architecture, introduced with the RISC System/6000 in early 1990. The design was inspired by earlier RISC processors such as IBM 801 and the MIPS architecture. The original POWER microprocessor, one of the first superscalar RISC implementations, was a high performance, multi-chip design. IBM soon realized that they would need a single-chip microprocessor to scale their RS/6000 line from lower-end to high-end machines, and work on a single-chip POWER microprocessor began. In early 1991 IBM realized that their design could potentially become a high-volume microprocessor used across the industry.

IBM approached Motorola with the goal of collaborating on the development of a family of single-chip microprocessors based on the POWER architecture. Soon after, Apple, as one of Motorola's largest customers of desktop-class microprocessors, joined the discussions. This three-way collaboration became known as AIM, for Apple, IBM, Motorola.

To Motorola, POWER looked like an unbelievable deal. It allowed them to sell a widely tested and powerful RISC CPU for little design cash on their own part. It also maintained ties with an important customer, Apple, and seemed to offer the possibility of adding another in IBM who might buy smaller versions from them instead of making their own.

At this point Motorola already had its own RISC design in the form of the 88000 which was doing poorly in the market. One oft-quoted reason for its failure was the lack of backward compatibility with their own famous 68000 series, also used in the Apple Macintosh.

However, the 88000 was already in production, and Apple (among others) already had machines running on it. If the new POWER single-chip solution could be made somewhat comparable at a hardware level with the 88000, that would allow both Apple and Motorola to bring machines to market much faster.

The result of these various requirements was the PowerPC (Performance Computing) specification. Everyone seems to have won:

  • IBM got the single-chip CPU they were looking for, largely for free
  • Apple got to use one of the most powerful RISC CPU's on the market, and massive press buzz due to IBM's name
  • Motorola got an up-to-date RISC chip for free, one with the potential to allow them to sell to many companies, including both Apple and IBM

Design features

The PowerPC is designed along RISC principles, and allows for a superscalar implementation. Versions of the design exist in both 32-bit and 64-bit implementations. Starting with the basic POWER specification, the PowerPC added:

  • Support for operation as in both Big-Endian and Little-Endian modes; the PowerPC can switch from one mode to the other at run-time (see below)
  • Single-precision forms of some floating point instructions, in addition to double-precision forms
  • Additional floating point instructions at the behest of Apple
  • A complete 64-bit specification, which is backward compatible with the 32-bit mode
  • Removal of some of the more esoteric POWER instructions, some of which could be emulated by the operating system if necessary.

Endian-modes

In Little-Endian mode, the three lowest-order bits of the effective address are exclusive-ORed with a three bit value selected by the length of the operand. This is not quite the same as being truly little-endian, and can cause problems when communicating with external devices.

In theory the byte order of the processor can be switched at run-time to support both Big- and Little-Endian programs simultaneously, and in fact it is possible to run a program in one mode and exception handlers (i.e. the operating system) in another. Practically speaking this would be difficult due to the interaction with external devices which have their own byte ordering.

An interesting side-effect of this implementation is that a program can store a 64-bit value (the longest operand format) to an address A while in one endian mode, switch modes, and when the value is read back from A it will be identical, even though ostensibly the processor is now in the opposite byte order mode.

Implementations

The first single-chip implementation of the design was the MPC601, a hybrid of the POWER1 and PowerPC specifications released in 1992. This allowed the chip to be used by IBM in their existing POWER1 based platforms, although it also meant some slight pain when switching to the 2nd generation "pure" PowerPC designs. Apple continued work on a new line of Macintosh computers based on the chip, and eventually released them as the 601-based Power Macintosh on March 14, 1994.

IBM also had a full line of PowerPC based desktops built and ready to ship; unfortunately they did not have an operating system ready. IBM decided to do a complete rewrite of OS/2 specifically for the PowerPC. Apple, who also lacked a PowerPC based OS, took a different route. They rewrote the essential pieces of the operating system and then wrote a 680x0 emulator which could run the remaining parts of the OS and 68K based applications. It took IBM 2 years to rewrite OS/2 for PowerPC and by then it was too late. The IBM PowerPC desktops never shipped. Byte magazine (April 1994) wrote an extensive article about the Apple and IBM PowerPC desktops.

The second generation was "pure" and included the "low end" 603 and "high end" 604. The 603 is notable due to its very low cost and power consumption. This was a deliberate design goal on Motorola's part, who used the 603 project to build the basic core for all future generations of PPC chips. Apple tried to use the 603 in a new laptop design but was unable to due to the small 8KB level 1 cache. The 68000 emulator in the Mac OS could not fit in 8KB and thus slowed the computer drastically. The 603e solved this problem by having a 16KB L1 cache which allowed the emulator to run efficiently.

The first 64-bit implementation was the 620, but it appears to have seen little use. It was later and slower than promised, and IBM used their own POWER3 design instead, offering no 64-bit "small" solution until the late-2002 introduction of the PowerPC 970. The 970 is a 64-bit processor derived from the POWER4 server processor. To create it, the POWER4 core was modified to be backwards-compatible with 32-bit PowerPC processors, and a vector unit (similar to the AltiVec extensions in Motorola's 74xx series) was added.

IBM's RS64 family is a modified PowerPC architecture. These processors are used in the RS/6000 and AS/400 computer families.

Numerically, the PowerPC is most found in controllers in cars. In this role, Motorola has offered up a huge number of versions built on the 603 core. To this they add various bits of custom hardware, to allow for I/O on the single chip.

Sonnet Technologies and Daystar manufacture PowerPC based cpu upgrades for use in Macintosh systems.

PowerPC processors are used in Apple Macintosh, IBM RS/6000 computer, the Pegasos (an Amiga spin off), Amiga acceleration boards, the Nintendo GameCube, and many embedded systems such as TiVo.

General-purpose PowerPC processors

PowerPC processors bring the processor's local bus to the chip's surface, and connect to a bridge chip that translate this into other on-board device buses that attach to RAM, PCI, and other devices.

  • 601 MPC601 50 and 66 MHz
  • 602 consumer products (multiplexed data/address bus)
  • 603 notebooks
  • 603e
  • 604
  • 604e
  • 620 the first 64-bit implementation
  • x704 BiCOMOS PowerPC implementation by Exponential Technologies
  • 750 (PowerPC G3) (1997) 233 MHz and 266 MHz, 740, 745, 755
  • 7400 (PowerPC G4) (1999) 350 MHz, 7410 uses AltiVec, a SIMD extension of the original PPC specs
  • 750FX announced by IBM in 2001 and available early 2002 at 1 GHz
  • 7450 microarchitecture family
  • 970 (PowerPC G5) (2003) 64-bit implementation derived from the IBM POWER4 enhanced with AltiVec, at speeds 1.4 GHz, 1.6 GHz, 1.8 GHz, 2.0 GHz and 2.5 GHz
  • Gekko 485 MHz (used in the Nintendo GameCube)
  • Power4+ IBM processor (clocking between 1.0 and 1.9 GHz) which powers the Regatta (RS/6000 or pSeries) servers

Embedded PowerPC Microcontrollers

32-bit PowerPC processors have been a favorite of embedded computer designers. To keep costs low on high-volume competitive products, the CPU core is usually bundled into a system-on-chip (SOC) integrated circuit. SOCs contain the processor core, cache and the processor's local data on-chip, along with with clocking, timers, memory (SDRAM), peripheral (network, serial I/O), and bus (PCI, PCI-X, ROM/Flash bus, I2C) controllers. IBM and Motorola have competed along parallel development lines in overlapping markets. A recent development is the BookE PowerPC Specification, implemented by both IBM and Motorola, which defines embedded extensions to the PowerPC programming model.

IBM:

  • 401
  • 403: MMU added in most advanced version 403GCX
  • 405: MMU, ethernet, serial, PCI, SRAM, SDRAM; NPe405 adds more network devices
  • 440GP: (BookE) MMU, multiple ethernet, serial, PCI-X, SRAM, SDRAM
  • 440GX: adds more SRAM/L2 cache

Motorola:

  • MPC 860/8xx (PowerQUICC): networking & telecomm card controllers
  • MPC 550/5xx line: (8xx core) automotive & industrial controllers
  • MPC 8260/82xx (PowerQUICC II) a 603 core, networking & telecomm system controllers with high-capacity onchip switched bus
  • MPC 8560/85xx (PowerQUICC III) a BookE core, networking & telecomm system controllers with even higher-capacity onchip bus

References

  • May, Cathy (editor) et.al. (1994). The PowerPC Architecture: A Specification for A New Family of RISC Processors. Morgan Kaufmann Publishers. ISBN 1-55860-316-6 (2nd ed.).
  • Hoxey, Steve (editor) et.al. The PowerPC Compiler Writer's Guide. Warthman Associates. ISBN 0-9649654-0-2.
  • Motorola. Programming Environments Manual for 32-bit Implementations of the PowerPC Architecture. P/N MPCFPE32B/AD .
  • IBM (2000). Book E: Enhanced PowerPC™ Architecture (3rd ed.)
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